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瑞萨科技开发微控制器用新型CPU架构

2007年05月22日 13:24:00 中国传动网

下一代架构将现存H8和M16C芯片特性与其他新科技相结合,为16位和32位MCU提供一个功能强大的综合解决方案 伦敦5月21日新闻――瑞萨科技公司今天宣布其正在开发一种新型CPU架构,这种架构将在密码安全,数据处理性能(MIPS/MHz)和功率消耗方面较前几代微控制器(MCUs)具有革命性的加强。瑞萨科技将基于新型架构提供两个CPU,指向开拓16位和32位MCU市场,同时保持与现存MCU兼容。该架构将为两种MCU提供升级,为瑞萨科技的MCU用户提供一种功能强大而引人注目的系统方案。 瑞萨科技目前提供的M16C和H8S 16位CPU和R32C 及H8SX 32位CPU新型架构将具有创新的进步。同时通过CPU指令组,外围设备寄存器组以及开发工具与现存CPU兼容。他将M16C和R32C CPU的优越代码效率与H8S和H8SX CPU的高速数据处理相结合。此外,新型CPU架构将进一步增强低功率消耗和低噪音的特性。拥有这些兼容性,瑞萨科技的目标是在代码效率,数据处理性能全球最佳性能(MIPS/MHz),功率消耗以及成本竞争力方面达到世界最佳水平。代码效率尤为重要,因为它通过使用更少的闪存空间帮助减小系统程序尺寸,降低系统整体成本。 通过该架构,瑞萨科技旨在将代码尺寸减小30%,CPU的功率消耗减少50%。 “由于功能强大的产品研发,经过现场验正的生产能力和丰富的系统开发环境,瑞萨的多种MCU产品已经多年在嵌入式市场取得成功,”瑞萨科技公司MCU业务部董事会主席兼总经理Hideharu Takebe说,“瑞萨的MCU每年赢得超过10,000项设计,在消费品,汽车系统,工业产品,办公设备以及通信产品应用领域不断获得认可。为了响应对16位和32位MCU产品不断增长的需求,下一步我们将为16位和32位MCU市场开发下一代简单架构CPU。宣布这个消息后,我们目前的和未来的客户可以相信瑞萨科技不仅致力于支持我们现存的MCU家族产品,也提供可靠的升级,瑞萨建立在其全球领先地位的基础至上,将继续引领MCU市场。 在瑞萨科技公司庆祝其成立四周年之际也正在进行下一代16位和32位CISC*³ CPU的开发。公司计划投入相当的资源到此项工程,预计新一代CPU将进一步扩展瑞萨科技的业务。 新型CPU开发 结合新型架构CPU的设备将涵盖16位和32位CISC性能,使用简单,并将缩短系统制造开发时间。此外,通过保持与现存产品的兼容性,新型CPU将使得目前的和将来的客户保持其工程投资。 瑞萨标准的开发环境,高性能的嵌入式工作站还将为其新型CPU和现存的MCU提供全面支持。这将简化移动现存产品中的软件资源到基于新型CPU的MCU,并将加速新软件的开发和调试。为了确保客户能得到多种开发工具的选择,瑞萨将根据其联盟合作计划继续与第三方公司合作,通过网络积极共享新型架构的信息。公司将继续开发新产品,运用目前的MCU产品为客户提供支持。2008年早期将推出新型CPU的规格,预计第二季度将推出配置新型CPU的设备:基于瑞萨的90nm闪存处理器的, CY2009。汽车应用设备预计将在非机动车应用设备推出后推出,推出时间由市场需求决定。 original text: [COLOR=#708090]Renesas Technology to develop new CPU architecture for microcontrollers The next-generation architecture will combine the features of the existing H8 and M16C cores along with other new technologies, delivering a powerful, comprehensive solution for 16- and 32-bit MCUs. LONDON, UK – 21st May 2007 — Renesas Technology Corp. today announced that it is in the process of developing a new CPU architecture that will provide revolutionary enhancements over previous generation microcontrollers (MCUs) in code-efficiency*¹, processing performance (MIPS/MHz), and power consumption. Based on the new architecture, Renesas will offer two CPUs to address 16- and 32-bit markets, while maintaining compatibility with Renesas‘ existing MCUs. The architecture will provide upgrade paths for both markets, delivering a powerful and compelling system solution for Renesas‘ MCU customers. The new architecture will have innovative advances over the M16C and H8S 16-bit CPUs and R32C and H8SX 32-bit CPUs that Renesas Technology currently offers, while offering compatibility with the existing families in terms of CPU instruction sets, peripheral register sets and development tools. It will combine the excellent code efficiency of the M16C and R32C CPUs with the high-speed data processing of the H8S and H8SX CPUs. Moreover, the new CPU architecture will further extend the low power consumption and low noise characteristics of both family lines. With these capabilities, Renesas aims to achieve the world‘s best overall performance considering code efficiency, processing performance (MIPS/MHz), power consumption and cost competitiveness. Code efficiency is especially important since it helps to minimize system program size and reduce overall system cost by allowing the use of less flash memory. By employing this new architecture, Renesas aims to reduce code size by 30% and CPU power dissipation by 50%. “Renesas‘ broad MCU product offerings have been successful in the embedded market for many years, backed by powerful product development, field-proven manufacturing capabilities and a rich system-development environment,” said Hideharu Takebe, board director and general manager, MCU business group, Renesas Technology Corp. “Renesas‘ MCUs have won over 10,000 designs annually, gaining accelerated acceptance in applications such as consumer products, automotive systems, industrial products, office equipment, and communication products. As a next step, we are developing next-generation CPUs for 16- and 32-bit markets under a single architecture, in response to the growing demand for both 16- and 32-bit MCU products. With this announcement, our present and future customers can be assured that Renesas is committed not only to supporting our existing MCU product families, but also to providing a solid upgrade path. Renesas continues to lead the MCU market by building on its global leadership. (No. 1 share*² worldwide)” The project to develop the next-generation 16- and 32-bit CISC*³ CPUs is underway as Renesas celebrates the fourth anniversary of its establishment. The company plans to dedicate substantial resources to the project, and the new CPUs are expected to further expand Renesas‘ MCU business. New CPU Development Devices incorporating CPUs based on the new architecture will scale from 16-bit to 32-bit CISC performance. They will be very easy to use and will shorten development times for system manufacturers. Moreover, by maintaining compatibility with existing products, the new CPUs will allow existing and future customers to preserve their engineering investments. Renesas‘ standard development environment, the High-performance Embedded Workshop, will also provide total support for the new CPUs as well as its existing MCUs. This will simplify the migration of software resources from the existing products to MCUs based on the new CPUs, and accelerate the development and debugging of new software. To ensure that customers will have access to a wide selection of development tools, Renesas will continue to work with third-party companies and actively share information concerning the new architecture via the Web under Renesas‘ Alliance Partner Program. The company will continue to develop new products and provide support for customers using currently available MCU products. The specifications of the new CPUs will be released in early 2008 and the first devices with the new CPUs are expected to become available during Q2, CY2009 based on Renesas‘ 90nm flash MCU process. Devices for automotive applications are expected to be introduced after those for non-automotive applications, with the schedule determined by market requirements.[/COLOR]
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