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瑞萨推出双核32-bit SuperH 微控制器

2007年04月28日 17:52:00 中国传动网

Renesas推出双核32-bit SuperH微控制器拥有960-MIPS操作性能和800 MFLOPS浮点操作性能 为消费者、工业、汽车音频/导航和多媒体应用提供的多用途设备包括:两个SH2A-FPU CPU核和全面的外围功能 瑞萨科技美国有限公司宣布五项新SuperH®32比特微控制器,可用于多核技术达到高级性能以满足许多内嵌系统的应用,如消费产品、工业设备和汽车音频和导航系统。SH7205 和 SH7265设备公司全并两个超标量体系结构的SH2A-FPU CPU核和一套片上外置设备,包括USB, ATAPI和图像处理功能。当双核微控制器在200 MHz最大操作频率情况下操作时,每一个CPU在Dhrystone v1.1基准操作性能下每秒执行4.8亿条指令,每秒执行4亿个浮点操作。 为满足必然的高功能和性能需求,新型微控制器使用接近基础而不同于传统方法的设计。在过去,过程节点用于提高密度整合和提高操作速度。今天,半导体技术已经达到可以利用相当可观的时间开发更好的制造过程节点。此外,现在的设计的解决方案用于解决各种难题,如增强的电流漏露率。 为避免这些问题,瑞萨针对在嵌入式应用中使用的微控制器开发了多核体系。其中一个主要的好处,就是在单芯片上植入多核CPU,由于CPU核可平行执行软件编码。针对内嵌式系统的多核IC被提前引进,主要应用于图像处理和相似多媒体产品的重载处理。相反地,SH7205和SH7265微控制器是多用途设备,目标瞄准在大范围要求高速即时控制应用上,处理性能等同于数字信号处理器芯片。 多核架构 SH7205和SH7265微控制器的多核体系在提供灵活性的同时尽可能地使性能达到高级。微控制器在过程性能不能退化且过程变得复杂和快速时,微控制器执行解决方案。应用在CPU核中的三个主要技术是: 国内使用单个特殊CPU多层体系架构的公交汽车系统。4层架构2层用于CPU的使用,别外两层用于DMAC使用。当公共汽车在使用另一个CPU的时候阻止了时间的浪费达到高速即时处理。 CPU核可处理不同的操作系统(OSs)或是在同一个上操作。如果一个CPU核正在运行µITRON OS,其它在运行µClinux OS,如他们可执行不同的程序。这种性能可使工程师们根据自己的操作状态和数据需要把系统变的更具灵活性。 CPU双核可直接与另外一个通话。每一个CPU可以检查另一个的状态,他们可以根据自己的需要利用记忆改变数据。因此,处理联接可通过共同调换他们各自的状态和数据在CPU之间执行。 芯片上的外围功能 外围功能的广泛排列,被植入在了SH7205和SH7265芯片中,减少了外部零件的需要,在利用最小成本的情况下创建高性能系统。包括:高速2.0USB标准接口,ATAPI接口和其它各种接口。设备拥有一个2D图形引擎和一个为用于图片处理的数字化音频输入端,以及用于图像输出和音频输出处理的类似RGB的WQVA (480x234-pixel)和QVA (320x240-pixel)输出端。 其它片上功能包括适用于电机控制系统的5-频道多功能记时器,双CAN控制器,8频道10比特A/D转换器,2频道8比特D/A转换器,监视时钟,针对速度提升音频应用的具备2空间容量的14频道DMAC等等。 除这些功能之外,SH7265针对AAC提供编码加速器用音频数据压缩。这种功能可以用于高速运行硬件或是类似AAC文档的创新。 original text [COLOR=#708090]Renesas Introduces Dual-core 32-bit SuperH Microcontrollers Capable of Up to 960-MIPS Processing Performance, 800 MFLOPS Floating-point Operation Performance General-purpose devices have two SH2A-FPU CPU cores and comprehensive peripheral functions for consumer, industrial, car audio/navigation, and multimedia applications. Renesas Technology America, Inc. today announced five new SuperH® 32-bit microcontrollers that use multi-core technology to achieve the high levels of performance required by many embedded system applications such as consumer products, industrial equipment, and car audio and navigation systems. The SH7205 and SH7265 devices incorporate two superscalar SH2A-FPU CPU cores and a comprehensive set of on-chip peripherals that includes USB, ATAPI, and image processing engine functions. When the dual-core microcontrollers are operating at their 200 MHz maximum operating frequency, each CPU delivers 480-MIPS (million instructions per second) processing performance in the Dhrystone v1.1 benchmark, and 400-MFLOPS (mega floating point number operations per second) floating-point operation performance. To meet inevitable demands for higher functionality and performance, the new microcontrollers use a design approach fundamentally different from the traditional method. In the past, generations of ever-finer process nodes have been used to improve integration density and increase operating speed. Today, however, semiconductor technology has reached the point where it takes considerable time to develop finer manufacturing process nodes. Moreover, fundamental limits of physics now mandate design solutions for an expanding variety of difficult problems, such as increased leakage current. To avoid these problems, Renesas developed a multi-core architecture for microcontrollers used in embedded applications. One of the main benefits of putting multiple CPU cores in a single chip is increased device performance because the CPU cores can execute lines of software code in parallel. The multi-core ICs for embedded systems previously introduced mostly have been aimed at image processing and similar multimedia products with heavy processing loads. By contrast, the SH7205 and SH7265 microcontrollers are general-purpose devices that target a broad span of applications requiring high-speed real-time control and processing performance equivalent to that of a digital signal processor (DSP) chip. Multi-core architecture The multi-core architecture of the SH7205 and SH7265 microcontrollers makes it possible to achieve high levels of performance while offering flexibility of use. The microcontrollers implemented a solution in which real-time processing performance does not degrade as processing becomes more complex and faster. The three main technologies in the CPU core’s design are: • The internal bus system uses a CPU-specific multi-layer structure. A 4-layer configuration provides two layers for CPU use and two for DMAC (direct memory access controller) use. This prevents time from being wasted while the bus is in use by the other CPU, for high-speed real-time processing. • The CPU cores can operate on different operating systems (OSs) or the same one. If one CPU core runs the µITRON OS, while the other runs the µClinux OS, for example, they can execute completely different programs. This capability lets engineers construct a system flexibly, according to its use or purpose. • The two CPU cores can communicate directly with each other. Each CPU can check the status of the other one, and they can exchange data using memory provided for that purpose. Thus, processing linkage can be implemented between the CPUs through mutual exchanges of their respective processing states and data. On-chip peripheral functions The extensive array of peripheral functions built into the SH7205 and SH7265 chips reduces the need for external parts and enables to create high-performance systems at less cost. They include a USB v2.0 High-Speed (480-Mbps) specification interface, ATAPI interface, and other various interfaces. The devices have a 2D graphic engine and a digital video input pin for graphic processing, and has WQVA-size (480x234-pixel) and QVA-size (320x240-pixel) analog RGB output pins for image and video output processing. Other on-chip functions include a 5-channel multifunction timer unit (MTU) suitable for motor control systems, 2-channel CAN controller, 8-channel 10-bit A/D converter, 2-channel 8-bit D/A converter, watchdog timer (WDT), 14-channel DMAC with 2-dimensional addressing capability for speeding up video applications, and more. Besides these functions, the SH7265 provides an encoding accelerator for AAC (Advanced Audio Coding) as the audio data compression method. This function can be used for high-speed hardware implementation of music data or similar AAC file creation.[/color]
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